For semiconductor integrated circuits (chips) such as memory devices, it can be cost effective to include multiple product configurations in one base design. For example, it would be desirable for a device to be capable of accommodating multiple output data configurations.
While memory devices typically perform a like function—storing data values for subsequent access, various data input/output configurations have been proposed. As a first example, the rate at which data can be accessed with a respect to a clock signal has given rise to single data rate (SDR) type designs, in which data is accessed once per clock cycle. At the same time, to increase throughput, double data rate (DDR) type designs are known which can access data twice per cycle (e.g., on rising and falling edge of clock cycle).
In order to better understand various aspects of the present invention, conventional output circuits for accommodating different clocking arrangements will now be described.
A first conventional output circuit for accommodating SDR timing is shown in FIG. 8A. FIG. 8A shows a conventional D-type “master-slave” flip-flop DFF 800. DFFs are often used as output registers in data communication product that output data in an SDR mode.
The DFF circuit 800 of FIG. 8A includes a master latch 802, a slave latch 804, and an output multiplexer (MUX) 806. A master latch 802 can include inverters I81 to I83, and passgates T81 and T82. Passgate T81 is enabled in response to an inverse clock signal CB, while passgate T82 is enabled in response to a clock signal C. In a similar fashion, a slave latch 804 can include inverters I84 to I86, and passgates T83 and T84. However, passgates T83 and T84 are enabled in the opposite fashion, with passgate T83 being enabled in response to clock signal C, while passgate T84 is enabled in response to inverse clock signal CB.
Complementary clock signals C and CB can be two de-skewed clock signals, typically generated from a single external clock. For simplicity, only a data path is shown in FIG. 8A.
In FIG. 8A, an output from master latch 802 can be provided to both a first input N81 of output MUX 806, as well as the input of slave latch 804. Slave latch 804 can have an output coupled to a second input N82 of output MUX 806. When inverse clock CB is low, output MUX 806 couples a first input N81 to a MUX output to provide an output value Q. Conversely, when clock signal C at an inverting control input is low, second input N82 can be coupled to the output of MUX 806 to provide the output value Q.
The operation of the circuit of FIG. 8A is shown in FIG. 8B. FIG. 8B is a timing diagram showing waveforms for clock signal C, inverted clock signal CB, an input data value DIN, MUX input node N81 and N82, and an output value Q.
Referring now to FIG. 8B in conjunction with FIG. 8A, prior to time t0, when inverse clock signal CB is high, master latch 802 can be in a “transparent” mode, allowing an input data value D<1> to propagate through to input N81. In addition, slave latch 804 can be in a latched mode, storing a previously received data value and preventing any input value from propagating through. In the example shown, a previous data value D<0> is latched within slave latch 804, and output as data value Q by way of second input N82.
At time t0, when clock signal C transitions high and inverse clock signal CB transitions low, master latch 802 can enter a latched state, latching data value D<1> and providing such a data value to node N81. Because inverse clock signal CB can be low, output MUX 806 can output data value D<1>. As a result, output value Q sees a change from the old bit D<0> to the new bit D<1>. At the same time, slave latch 804 can enter a transparent mode, allowing data value D<1> to propagate through to node N82.
At time t1, clock signal transitions from high to low. As a result, slave latch 804 can go into a latched mode, and continue to output data value D<1>. Because clock signal C goes low, data value D<1> at second input node ND2 can be provided as output value Q.
Operations can continue in this manner to provide a different output value each clock cycle.
In contrast to SDR type operations described above, in a DDR device, such as a DDR memory device, a 2-to-1 parallel-in-serial-out (PISO) type circuit is often used as an output register. A 2-to-1 PISO can convert 2-bit parallel data to 1-bit serial data at double data rate.
One example of a conventional 2-to-1 PISO is shown in FIG. 9A, and designated by the general reference character 900. A 2-to-1 PISO can include two DFFs 902-0 and 902-1 and an output MUX 904. A first DFF 902-0 can receive a first input data value DH and provide an output value on a node N91. Similarly, second DFF 902-1 can receive a second input data value DL and provide an output value on a node N92. First DFF 902-0 operates in response to clock signal C, while second DFF 902 operates in response to inverse clock signal CB.
As understood from the figure, when clock signal C is low, output MUX 904 couples a first input N91 to a MUX the output to provide an output value DOUT. When inverse clock signal CB at an inverting control input is low, second input N92 can be coupled to the output of MUX 904 to provide the output value DOUT.
As in case of the SDR arrangement in FIG. 8A, complementary clock signals C and CB can be two de-skewed clock signals, typically generated from a single external clock. In addition, only a data path is shown in FIG. 9A to avoid cluttering the view.
The operation of the circuit of FIG. 9A is shown in FIG. 9B. FIG. 9B is a timing diagram showing waveforms for clock signal C, inverted clock signal CB, first and second input data values DH and DL, nodes N91 and N92 of output MUX 904, and an output value DOUT.
As understood from FIGS. 9A and 9B, both DFFs (902-0 and 902-1) are edge-triggered registers. When clock signal C switches from low to high and inverse clock signal switches from high to low, output MUX 904 can select a data value at node N91 to pass through and output as DOUT. At the same time, first DFF 902-0 can latch a first input value DH and provide it at node N91. When clock signal C switches from high to low, and inverse clock switches from low to high, output MUX 904 can select node N91 to pass through as output DOUT. Second DFF 902-1 can then latch a second input value DL, and provide it at node N92.
In the arrangement of FIGS. 9A and 9B, it can be critical to have clock signals (e.g., C and CB) routed in the reverse direction with respect to a flow of data through the circuit. This can ensure that output MUX 904 switches (i.e., outputs) node N91 before node N92 is updated by an incoming data value, and vice versa.
In conventional approaches, providing for SDR and DDR timing for a same type of device is typically accomplished by separate circuits (i.e., a DFF for an SDR mode and a 2-to-1 PISO for DDR mode). While it is possible to reuse an existing DFF from within a 2-to-1 PISO in order to provide a DFF for an SDR mode, such an arrangement typically requires a more complicated multiplexing scheme. Further, in such an arrangement, the components of the 2-to-1 PISO are not used efficiently, thus wasting space on the device.
In light of the above, it would be desirable to arrive at a single circuit that can support both SDR and DDR modes of operation.
It would also be desirable that such a single circuit is selectable between such modes by a simple manufacturing option.
It would also be desirable that such a single circuit be comparable to a DFF in terms of area and speed.